Freescale Semiconductor /MK60DZ10 /ENET /TCSR3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TCSR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TDRE 0 (0000)TMODE0 (0)TIE 0 (0)TF

TIE=0, TMODE=0000, TF=0, TDRE=0

Description

Timer Control Status Register

Fields

TDRE

Timer DMA Request Enable

0 (0): DMA request is disabled

1 (1): DMA request is enabled

TMODE

Timer Mode

0 (0000): Timer Channel is disabled.

1 (0001): Timer Channel is configured for Input Capture on rising edge

2 (0010): Timer Channel is configured for Input Capture on falling edge

3 (0011): Timer Channel is configured for Input Capture on both edges

4 (0100): Timer Channel is configured for Output Compare - software only

5 (0101): Timer Channel is configured for Output Compare - toggle output on compare

6 (0110): Timer Channel is configured for Output Compare - clear output on compare

7 (0111): Timer Channel is configured for Output Compare - set output on compare

9 (10x1): Timer Channel is configured for Output Compare - set output on compare, clear output on overflow

10 (1010): Timer Channel is configured for Output Compare - clear output on compare, set output on overflow

14 (1110): Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle

15 (1111): Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle

TIE

Timer interrupt enable

0 (0): Interrupt is disabled

1 (1): Interrupt is enabled

TF

Timer Flag

0 (0): Input Capture or Output Compare has not occurred

1 (1): Input Capture or Output Compare has occurred

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